1. Technical Field
The present invention relates to software tools in general, and, in particular, to software tools for verifying integrated circuit designs. Still more particularly, the present invention relates to a method and system for performing static timing analysis on digital electronic circuits.
2. Description of Related Art
In the field of integrated circuit (IC) design, digital electronic circuits are initially represented by a high-level abstraction written in hardware description language (HDL).
The HDL representation allows a circuit designer to express all the desired functionality of a digital electronic circuit at the register transfer level (RTL) of abstraction.
The HDL representation is then converted into a circuit file through a process known as synthesis that involves translation and optimization. Finally, static timing analysis and formal verification are performed on the circuit file. Static timing analysis verifies that the circuit design performs at target clock speeds. Formal verification ensures that the circuit file is functionally correct compared to the HDL.
In order to simplify static timing analysis, circuit designers commonly identify and eliminate a selected set of non-critical timing paths throughout a circuit design when performing static timing analysis on the circuit design. Such set of non-critical timing paths is usually called a snip (or exception) file. For most circuit designs, such practice is usually done to eliminate false timing violations during static timing analysis. However, when the critical timing paths of some circuit designs are masked as part of the cone of logic of the eliminated non-critical timing paths, the elimination of the non-critical timing paths could lead to a real timing violation to go undetected during static timing analysis. The real timing violation may not even be realized until actual hardware is manufactured. Consequently, it would be desirable to provide an improved method for performing static timing analysis on digital electronic circuits.